The present invention relates to a circuit for a memory cell circuit and, more particularly, to an address selection circuit for a memory cell circuit.
A conventional memory cell circuit comprised a plurality of memory cells aligned in a matrix shape having a number of rows and columns. In response to a selected combination of row and column address selection signals, only one memory cell was selected, for inputting and outputting data signals. An address selection circuit was connected to the memory cell circuit for addressing through the application of addressing signals. Conventionally, the address selection circuit comprised some AND gates having the addressing signals as inputs.
Chip selection enabling signals were provided for placing the memory cell circuit in a chip selection condition wherein one of the memory cells was selected for addressing purposes by a row addressing signal and a column addressing signal. The chip selection enabling signals were applied to all of the AND gates, thereby making the address selection circuit complicated due to the necessity of an additional circuit configuration therefor.
Therefore, it was desired that the address selection circuit be simplified as much as possible.